USBDEV DV document
Goals
- DV
- Verify all USBDEV IP features by running dynamic simulations with a SV/UVM based testbench.
- Develop and run all tests based on the DV plan below towards closing code and functional coverage on the IP and all of its sub-modules.
- Note that code and functional coverage goals are TBD due to pending evaluation of where / how to source a USB20 UVM VIP.
- The decision is trending towards hooking up a cocotb (Python) based open source USB20 compliance test suite with this UVM environment.
- FPV
- Verify TileLink device protocol compliance with an SVA based testbench.
Current status
Design features
For detailed information on USBDEV design features, please see the USBDEV HWIP technical specification.
Testbench architecture
USBDEV testbench has been constructed based on the CIP testbench architecture.
Block diagram
Top level testbench
Top level testbench is located at hw/ip/usbdev/dv/tb/tb.sv
.
It instantiates the USBDEV DUT module hw/ip/usbdev/rtl/usbdev.sv
.
In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into uvm_config_db
:
- Clock and reset interface for the TL and USB domains
- TileLink host interface
- USBDEV IOs
- Interrupts (
pins_if
Common DV utility components
The following utilities provide generic helper tasks and functions to perform activities that are common across the project:
Compile-time configurations
None for now.
Global types & methods
All common types and methods defined at the package level can be found in usbdev_env_pkg
.
Some of them in use are:
[list a few parameters, types & methods; no need to mention all]
TL_agent
USBDEV testbench instantiates (already handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into USBDEV device.
USB20 Agent
The usb20_agent is currently a skeleton implementation. It does not offer any functionality yet.
UVM RAL Model
The USBDEV RAL model is created with the ralgen
FuseSoC generator script automatically when the simulation is at the build stage.
It can be created manually by invoking regtool
:
Reference models
There are no reference models in use currently.
Stimulus strategy
Test sequences
All test sequences reside in hw/ip/usbdev/dv/env/seq_lib
.
The usbdev_base_vseq
virtual sequence is extended from cip_base_vseq
and serves as a starting point.
All test sequences are extended from usbdev_base_vseq
.
It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call.
Some of the most commonly used tasks / functions are as follows:
usbdev_init()
: Do basic USB device initialization.
Functional coverage
To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:
- TBD
Self-checking strategy
Scoreboard
The usbdev_scoreboard
is primarily used for end to end checking.
It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:
- TBD
Assertions
- TLUL assertions: The
tb/usbdev_bind.sv
binds thetlul_assert
assertions to the IP to ensure TileLink interface protocol compliance. - Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
- TBD
Building and running tests
We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a smoke test:
$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/usbdev/dv/usbdev_sim_cfg.hjson -i usbdev_smoke
DV plan
Milestone | Name | Description | Tests |
---|---|---|---|
V1 | smoke | Goal: Smoke test accessing a major datapath in USBDEV. Stimulus: Describe the stimulus procedure. Checks": Describe the self-check procedure.
Start a new paragraph. | usbdev_smoke |
V1 | csr_hw_reset | Verify the reset values as indicated in the RAL specification.
| usbdev_csr_hw_reset |
V1 | csr_rw | Verify accessibility of CSRs as indicated in the RAL specification.
| usbdev_csr_rw |
V1 | csr_bit_bash | Verify no aliasing within individual bits of a CSR.
| usbdev_csr_bit_bash |
V1 | csr_aliasing | Verify no aliasing within the CSR address space.
| usbdev_csr_aliasing |
V1 | csr_mem_rw_with_rand_reset | Verify random reset during CSR/memory access.
| usbdev_csr_mem_rw_with_rand_reset |
V1 | mem_walk | Verify accessibility of all memories in the design.
| usbdev_mem_walk |
V1 | mem_partial_access | Verify partial-accessibility of all memories in the design.
| usbdev_mem_partial_access |
V2 | intr_test | Verify common intr_test CSRs that allows SW to mock-inject interrupts.
| usbdev_intr_test |
V2 | tl_d_oob_addr_access | Access out of bounds address and verify correctness of response / behavior | usbdev_tl_errors |
V2 | tl_d_illegal_access | Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested
| usbdev_tl_errors |
V2 | tl_d_outstanding_access | Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address. | usbdev_csr_hw_reset usbdev_csr_rw usbdev_csr_aliasing usbdev_same_csr_outstanding |
V2 | tl_d_partial_access | Access CSR with one or more bytes of data For read, expect to return all word value of the CSR For write, enabling bytes should cover all CSR valid fields | usbdev_csr_hw_reset usbdev_csr_rw usbdev_csr_aliasing usbdev_same_csr_outstanding |