USBDEV DV Plan
- Verify all USBDEV IP features by running dynamic simulations with a SV/UVM based testbench.
- Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP and all of its sub-modules.
- Note that code and functional coverage goals are TBD due to pending evaluation of where / how to source a USB20 UVM VIP.
- The decision is trending towards hooking up a cocotb (Python) based open source USB20 compliance test suite with this UVM environment.
- Verify TileLink device protocol compliance with an SVA based testbench.
For detailed information on USBDEV design features, please see the USBDEV HWIP technical specification.
USBDEV testbench has been constructed based on the CIP testbench architecture.
Top level testbench
Top level testbench is located at
It instantiates the USBDEV DUT module
In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into
- Clock and reset interface for the TL and USB domains
- TileLink host interface
- USBDEV IOs
- Interrupts (
Common DV utility components
The following utilities provide generic helper tasks and functions to perform activities that are common across the project:
None for now.
Global types & methods
All common types and methods defined at the package level can be found in
Some of them in use are:
[list a few parameters, types & methods; no need to mention all]
USBDEV testbench instantiates (already handled in CIP base env) tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into USBDEV device.
The usb20_agent is currently a skeleton implementation. It does not offer any functionality yet.
UVM RAL Model
The USBDEV RAL model is created with the
ralgen FuseSoC generator script automatically when the simulation is at the build stage.
It can be created manually (separately) by running
make in the the
There are no reference models in use currently.
All test sequences reside in
usbdev_base_vseq virtual sequence is extended from
cip_base_vseq and serves as a starting point.
All test sequences are extended from
It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call.
Some of the most commonly used tasks / functions are as follows:
usbdev_init(): Do basic USB device initialization.
To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:
usbdev_scoreboard is primarily used for end to end checking.
It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:
- TLUL assertions: The
tlul_assertassertions to the IP to ensure TileLink interface protocol compliance.
- Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
Building and running tests
We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here's how to run a basic sanity test:
$ cd hw/ip/usbdev/dv $ make TEST_NAME=usbdev_sanity
Goal: Basic sanity test acessing a major datapath in USBDEV.
Stimulus: Describe the stimulus procedure.
Checks": Describe the self-check procedure.
Start a new paragraph.
Verify the reset values as indicated in the RAL specification.
Verify accessibility of CSRs as indicated in the RAL specification.
Verify no aliasing within individual bits of a CSR.
Verify no aliasing within the CSR address space.
Verify accessibility of all memories in the design.
Verify partial-accessibility of all memories in the design.
Verify common intr_test CSRs that allows SW to mock-inject interrupts.
Access out of bounds address and verify correctness of response / behavior
Drive unsupported requests via TL interface and verify correctness of response / behavior
Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.
Do partial accesses.