USB UART HWIP Technical Specification

Overview

This document specifies the USB UART hardware IP functionality. This module conforms to the Comportable guideline for peripheral functionality. See that document for integration overview within the broader top level system.

Features

  • External full speed USB device interface with UART interface to CPU
  • Software developed for the Comportable UART should work without changes
  • Enumerates as Google Simple Serial interface (has host USB stack support)
  • 8-bit data word
  • Serial line settings (baud rate, parity, stop bits) are ignored, the interface directly forms or consumes USB pakets
  • 32 x 8b RX buffer
  • 32 x 8b TX buffer
  • Interrupt for overflow, break error, receive timeout. Frame and parity errors will not happen but may be configured.

Description

The USBUART module is a USB Full Speed device interface that presents the standard Comportable UART interface to the system. The serial line settings (baud rate, parity, stop bits) are ignored and the 8-bit characters flow directly over the Google USB Simple Serial Class interface.

Compatibility

The UART is compatible with the interface provided by the Comportable UART.

Theory of Operations

The register inteface to the USBUART matches the standard UART. There are two additional registers USBSTAT and USBPARAM that provide information about the USB interface that may be useful for software that knows this is more than the simple uart. In particular when the interface is used to bridge from USB to a real uart interface (for example for Case closed debugging) the requested Baud rate and parity may be read.

Block Diagram

UART Block Diagram

Hardware Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module usbuart has the following hardware interfaces defined.

Primary Clock: clk_fixed

Other Clocks:

Bus Device Interface: tlul

Bus Host Interface: none

Peripheral Pins for Chip IO:

Pin namedirectionDescription
usb_senseinputUSB host VBUS sense
usb_pullupoutputUSB FS pullup control
usb_dpinoutUSB data D+
usb_dminoutUSB data D-

Interrupts:

Interrupt NameDescription
tx_watermarkraised if the transmit FIFO is past the highwater mark.
rx_watermarkraised if the receive FIFO is past the highwater mark.
tx_overflowraised if the transmit FIFO has overflowed.
rx_overflowraised if the receive FIFO has overflowed.
rx_frame_errraised if a framing error has been detected on receive, which will never happen on the USB interface.
rx_break_errraised if break condition has been detected on receive. This is done if either the host is not providing VBUS or has not provided a Start of Frame indication in 2.048ms.
rx_timeoutraised if RX FIFO has characters remaining in the FIFO without being retrieved for the programmed time period.
rx_parity_errraised if the receiver has detected a parity error, which will never happen on the USB interface.

Security Alerts:

Alert NameDescription

Design Details

USB interface

The USB device interface supports only Full Speed (12Mb) operation and complies with the USB2.0 standard using the Google Simple Stream class. The USB physical interface is implemented using two general 3.3V I/O pins for the USB D+/D- wires. These should be connected through 22-48 Ohm series resistors to the USB connector (exact value and SI depends on the implementation and the resistor could be incorporated in the output driver if the implementation allows).

The USB FS interface needs a 1.5kOhm pullup to 3.3V on the D+ wire to indicate the presenece of the peripheral. This resistor is connected between the D+ line and the 3.3V usb_pullup output pin, so the device is disconnected until the pin is driven high. This is done when either the UART transmit or receive interface is enabled.

The Host of the USB connection may remove VBUS to signal a disconnection (either because an actual disconnection of the cable happened, or because the host is attempting to hard reset the device). This is detected on the usb_sense input which should signal the presence of VBUS. Depending on the implementation the chip pin may connect directly to VBUS (5V logic) or be connected using a resisor divider.

The implementation provides the USB end-point zero descriptors required (with no strings provided), OUT endpoint 1 that carries data from the host as though received by the UART and IN endpoint 1 that is used to transmit data from the UART transmit fifo to the host. Endpoint 1 will respond to SETUP packets to allow the host to read or write the baud rate and parity passed in the USBPARAM register. (Note the current software implementation only implements the host writing these, so for portability it is best to avoid reads at this time.)

Transmission

Just as in the standard UART, a write to WDATA enqueues a data byte into the 32 depth write FIFO. Characters will be moved from the fifo to be available to send when an IN request is received from the host on endpoint 1. The interface attempts to gather characters. An IN transaction will be initiated either when a full USB packet (32 bytes) is ready or if there are characters pending and no additional characters have been queued by software for 3-4us.

Reception

Characters received from the OUT endpoint are inserted in to the 32-byte receive FIFO. Backpressure is applied to the host if the receive FIFO does not have room for a full USB packet. The received data can be read from the RDATA register.

Interrupts

UART module has a few interrupts including general data flow interrupts and unexpected event interrupts.

If TX or RX FIFO hits designated depth of entries, txint or rxint signal is raised to inform FW. FW can configure the watermark value FIFO_CTRL.RXILVL or FIFO_CTRL.TXILVL .

In any case, if any FIFO receives write request when FIFO is full, tx_overflow or rx_overflow interrupts is asserted.

intr_rx_frame_err signal is not used.

A break condition is signalled if either the VBUS is removed or the host has not sent a Start-of-Frame for 2.048ms (an SOF should happen every 1ms).

Programmers Guide

Initialization

The UART does not need initialization (default is for usb_pullup to be applied). However, since the settings will be ignored it is possible to run the initialization sequence for the standard UART.

Common Examples

Do the following to transmit a string of characters.

int uart_tx_rdy() {
  return ((*UART_FIFO_STATUS_REG & UART_FIFO_STATUS_TXLVL_MASK) == 32) ? 0 : 1;
}

void uart_send_char(char val) {
  while(!uart_tx_rdy()) {}
  *UART_WDATA_REG = val;
}

void uart_send_str(char *str) {
  while(*str != \0) {
    uart_send_char(*str++);
}

Do the following to receive a character, with -1 returned if RX is empty.

int uart_rx_empty() {
  return ((*UART_FIFO_STATUS_REG & UART_FIFO_STATUS_RXLVL_MASK) == (0 << 6)) ? 1 : 0;
}

char uart_rcv_char() {
  if(uart_rx_empty())
    return 0xff;
  return *UART_RDATA_REG;
}

Interrupt Handling

void uart_interrupt_routine() {
  volatile uint32 is = *UART_INTR_REG;
  uint32 is_mask = 0;
  char uart_ch;
  uint32 ien_reg;

  // Turn off Interrupt Enable
  ien_reg = *UART_IEN_REG;
  *UART_IEN_REG = ien_reg & 0xFFFFFF00; // Clr bit 7:0

  if (is & UART_INTR_RXPE_MASK) {
    // Do something ...

    // Store Int mask
    is_mask |= UART_INTR_RXPE_MASK;
  }

  if (is & UART_INTR_RXB_MASK) {
    // Do something ...

    // Store Int mask
    is_mask |= UART_INTR_RXB_MASK;
  }

  // .. Frame Error

  // TX/RX Overflow Error

  // RX Int
  if (is & UART_INTR_RX_MASK) {
    while(1) {
      uart_ch = uart_rcv_char();
      if (uart_ch == 0xff) break;
      uart_buf.append(uart_ch);
    }
    // Store Int mask
    is_mask |= UART_INTR_RX_MASK;
  }

  // Clear ISTATE
  *UART_INTR_REG = is_mask;

  // Restore ICTRL
  *UART_IEN_REG = ictrl_reg ;
}

Register Table

usbuart.INTR_STATE @ + 0x0
Interrupt State Register
Reset default = 0x0, mask 0xff
31302928272625242322212019181716
 
1514131211109876543210
  rx_parity_err rx_timeout rx_break_err rx_frame_err rx_overflow tx_overflow rx_watermark tx_watermark
BitsTypeResetNameDescription
0rw1c0x0tx_watermarkraised if the transmit FIFO is past the highwater mark.
1rw1c0x0rx_watermarkraised if the receive FIFO is past the highwater mark.
2rw1c0x0tx_overflowraised if the transmit FIFO has overflowed.
3rw1c0x0rx_overflowraised if the receive FIFO has overflowed.
4rw1c0x0rx_frame_errraised if a framing error has been detected on receive, which will never happen on the USB interface.
5rw1c0x0rx_break_errraised if break condition has been detected on receive. This is done if either the host is not providing VBUS or has not provided a Start of Frame indication in 2.048ms.
6rw1c0x0rx_timeoutraised if RX FIFO has characters remaining in the FIFO without being retrieved for the programmed time period.
7rw1c0x0rx_parity_errraised if the receiver has detected a parity error, which will never happen on the USB interface.


usbuart.INTR_ENABLE @ + 0x4
Interrupt Enable Register
Reset default = 0x0, mask 0xff
31302928272625242322212019181716
 
1514131211109876543210
  rx_parity_err rx_timeout rx_break_err rx_frame_err rx_overflow tx_overflow rx_watermark tx_watermark
BitsTypeResetNameDescription
0rw0x0tx_watermarkEnable interrupt when INTR_STATE.tx_watermark is set
1rw0x0rx_watermarkEnable interrupt when INTR_STATE.rx_watermark is set
2rw0x0tx_overflowEnable interrupt when INTR_STATE.tx_overflow is set
3rw0x0rx_overflowEnable interrupt when INTR_STATE.rx_overflow is set
4rw0x0rx_frame_errEnable interrupt when INTR_STATE.rx_frame_err is set
5rw0x0rx_break_errEnable interrupt when INTR_STATE.rx_break_err is set
6rw0x0rx_timeoutEnable interrupt when INTR_STATE.rx_timeout is set
7rw0x0rx_parity_errEnable interrupt when INTR_STATE.rx_parity_err is set


usbuart.INTR_TEST @ + 0x8
Interrupt Test Register
Reset default = 0x0, mask 0xff
31302928272625242322212019181716
 
1514131211109876543210
  rx_parity_err rx_timeout rx_break_err rx_frame_err rx_overflow tx_overflow rx_watermark tx_watermark
BitsTypeResetNameDescription
0wo0x0tx_watermarkWrite 1 to force INTR_STATE.tx_watermark to 1
1wo0x0rx_watermarkWrite 1 to force INTR_STATE.rx_watermark to 1
2wo0x0tx_overflowWrite 1 to force INTR_STATE.tx_overflow to 1
3wo0x0rx_overflowWrite 1 to force INTR_STATE.rx_overflow to 1
4wo0x0rx_frame_errWrite 1 to force INTR_STATE.rx_frame_err to 1
5wo0x0rx_break_errWrite 1 to force INTR_STATE.rx_break_err to 1
6wo0x0rx_timeoutWrite 1 to force INTR_STATE.rx_timeout to 1
7wo0x0rx_parity_errWrite 1 to force INTR_STATE.rx_parity_err to 1


usbuart.CTRL @ + 0xc
UART control register
Reset default = 0x0, mask 0xffff03f7
31302928272625242322212019181716
NCO
1514131211109876543210
  RXBLVL PARITY_ODD PARITY_EN LLPBK SLPBK   NF RX TX
BitsTypeResetNameDescription
0rw0x0TXTX enable, if this bit is set (or the RX) the USB interface is enabled by asserting the usb_pullup.
1rw0x0RXRX enable, if this bit is set (or the TX) the USB interface is enabled by asserting the usb_pullup.
2rw0x0NFIgnored (RX noise filter enable)
3Reserved
4rw0x0SLPBKSystem loopback enable If this bit is turned on, bytes written to the tx fifo will loop back to the rx fifo. They will be syncronized through the USB 48MHz clock domain. When in loopback the USB interface will always see an empty TX fifo so will never send any data, and all data received on the USB interface is discarded.
5rw0x0LLPBKIgnored (Line loopback enable)
6rw0x0PARITY_ENIgnored (Parity enable)
7rw0x0PARITY_ODDIgnored (1 for odd parity, 0 for even.)
9:8rw0x0RXBLVLTrigger level for rx break detection. A break is detected whenever the USB Host VBUS is dropped or if the host stops sending Start of Frame packets (which should arrive every 1ms). If this field is 0 then the break is detected if no SOF is received for 2.048ms, if non-zero then when no SOF is received for 1s.
15:10Reserved
31:16rw0x0NCOBAUD clock rate control. This is only used to determine the bit time used as the basis for the RX timeout, so the software will see the same timeout time as if configuring the standard uart (see TIMEOUT_CTRL register).


usbuart.STATUS @ + 0x10
UART live status register
Reset default = 0x0, mask 0x3f
31302928272625242322212019181716
 
1514131211109876543210
  RXEMPTY RXIDLE TXIDLE TXEMPTY RXFULL TXFULL
BitsTypeResetNameDescription
0ro0x0TXFULLTX buffer is full
1ro0x0RXFULLRX buffer is full
2ro0x0TXEMPTYTX FIFO is empty
3ro0x0TXIDLETX is idle. At the moment this matches the TXEMPTY bit.
4ro0x0RXIDLERX is idle. At the moment this matches the RXEMPTY bit.
5ro0x0RXEMPTYRX FIFO is empty


usbuart.RDATA @ + 0x14
UART read data
Reset default = 0x0, mask 0xff
31302928272625242322212019181716
 
1514131211109876543210
  RDATA
BitsTypeResetNameDescription
7:0ro0x0RDATA


usbuart.WDATA @ + 0x18
UART write data
Reset default = 0x0, mask 0x0
31302928272625242322212019181716
 
1514131211109876543210
  WDATA
BitsTypeResetNameDescription
7:0woxWDATA


usbuart.FIFO_CTRL @ + 0x1c
UART FIFO control register
Reset default = 0x0, mask 0x7f
31302928272625242322212019181716
 
1514131211109876543210
  TXILVL RXILVL TXRST RXRST
BitsTypeResetNameDescription
0rw0x0RXRSTRX fifo reset
1rw0x0TXRSTTX fifo reset
4:2rw0x0RXILVLTrigger level for RX interrupts
0rxlvl11 character
1rxlvl44 characters
2rxlvl88 characters
3rxlvl1616 characters
4rxlvl3030 characters
Other values are reserved.
6:5rw0x0TXILVLTrigger level for TX interrupts
0txlvl11 character
1txlvl44 characters
2txlvl88 characters
3txlvl1616 characters


usbuart.FIFO_STATUS @ + 0x20
UART FIFO status register
Reset default = 0x0, mask 0x3f003f
31302928272625242322212019181716
  RXLVL
1514131211109876543210
  TXLVL
BitsTypeResetNameDescription
5:0ro0x0TXLVLCurrent fill level of TX fifo
15:6Reserved
21:16ro0x0RXLVLCurrent fill level of RX fifo


usbuart.OVRD @ + 0x24
UART override control register
Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  TXVAL TXEN
BitsTypeResetNameDescription
0rw0x0TXENIgnored (Override the TX signal)
1rw0x0TXVALIgnored (Value for TX Override)


usbuart.VAL @ + 0x28
UART oversampled values
Reset default = 0x0, mask 0xffff
31302928272625242322212019181716
 
1514131211109876543210
RX
BitsTypeResetNameDescription
15:0ro0x0RXAlways zero (Last 16 oversampled values of RX.)


usbuart.TIMEOUT_CTRL @ + 0x2c
UART RX timeout control
Reset default = 0x0, mask 0x80ffffff
31302928272625242322212019181716
EN   VAL...
1514131211109876543210
...VAL
BitsTypeResetNameDescription
23:0rw0x0VALRX timeout value in UART bit times
30:24Reserved
31rw0x0ENEnable RX timeout feature


usbuart.USBSTAT @ + 0x30
USB Status
Reset default = 0x0, mask 0x7fc7ff
31302928272625242322212019181716
  device_address
1514131211109876543210
host_lost host_timeout   frame
BitsTypeResetNameDescription
10:0ro0x0frameFrame index received from host. On an active link this will increment every milisecond.
13:11Reserved
14ro0x0host_timeoutStart of frame not received from host for 1s.
15ro0x0host_lostStart of frame not received from host for 2.048ms.
22:16ro0x0device_addressDevice address set by host.


usbuart.USBPARAM @ + 0x34
USB Parmeters
Reset default = 0x0, mask 0x3ffff
31302928272625242322212019181716
  parity_req
1514131211109876543210
baud_req
BitsTypeResetNameDescription
15:0ro0x0baud_reqBaud rate requested if the interface is bridged to a real uart.
17:16ro0x0parity_reqParity requested if the interface is bridged to a real uart.
0noneNo parity
1oddOdd parity
2evenEven parity
Other values are reserved.