Earlgrey Chip DV document
Goals
- DV
- Verify
top_earlgrey
features by running dynamic simulations with a SV/UVM based testbench. - Verify the integration of all pre-verified IPs instantiated in the chip.
- Verify the integration and the internal design of non-pre-verified IPs instantiated in the chip.
- Verify system level scenarios for correctness of our design assumptions and behavior.
- Verify the full chip configuration and memory address space by running the automated tests.
- Stress test the XBAR structures in the chip.
- Verify
- FPV
- Verify the connectivity of signals (that are excluded from functional DV above) from point A to point B.
- Secure verification
- Check for leakage of secure data into unsecure locations / paths and vice-versa using the Cadence SPV tool.
Current status
Design features
For detailed information on top_earlgrey
design features, please see the Earl Grey Top Level Specification.
Testbench architecture
The top_earlgrey
chip level testbench has been constructed based on the CIP testbench architecture.
Block diagram
TBD
Top level testbench
Top level testbench is located at hw/ip/top_earlgrey/dv/tb/tb.sv
.
It instantiates the top_earlgrey
DUT module hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv
.
In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into uvm_config_db
:
- Clock and reset interface
- Main clock as well as USB clock
- TileLink host interface
- This is connected to the CPU’s data port.
- JTAG interface
- SPI interface
- UART interface
- SW logger inteface (for test boot ROM as well as the test SW)
- SW test status monitor
- Backdoor memory interfaces (for ROM, SRAM and the flask banks)
- Individual control pins:
- Bootstrap
- JTAG/SPI switch
- SRST_N
Common DV utility components
The following utilities provide generic helper tasks and functions to perform activities that are common across the project:
Global types & methods
All common types and methods defined at the package level can be found in the chip_env_pkg
.
Some of them in use are:
[list a few parameters, types & methods; no need to mention all]
TL_agent
The full chip testbench instantiates (already handled in CIP base env) the tl_agent which provides the ability to drive and independently monitor random traffic via TL host interface into CHIP device.
UART Agent
[Describe here or add link to its README]
SPI Agent
[Describe here or add link to its README]
JTAG Agent
[Describe here or add link to its README]
I2C Agent
[Describe here or add link to its README]
USB20 Agent
[Describe here or add link to its README]
UVM RAL Model
The CHIP RAL model is created with the ralgen
FuseSoC generator script automatically when the simulation is at the build stage.
It can be created manually (separately) by running make
in the the hw/
area.
Reference models
Testbench configurations
Stub CPU mode
Bare-metal SW test mode
XBAR integration mode
Stimulus strategy
Test sequences
All test sequences reside in hw/ip/chip/dv/env/seq_lib
.
The chip_base_vseq
virtual sequence is extended from cip_base_vseq
and serves as a starting point.
All test sequences are extended from chip_base_vseq
.
It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call.
Some of the most commonly used tasks / functions are as follows:
- task 1:
- task 2:
Functional coverage
To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:
- cg1:
- cg2:
Self-checking strategy
Scoreboard
The chip_scoreboard
is primarily used for end to end checking.
It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:
- analysis port1:
- analysis port2:
Assertions
- TLUL assertions: The
tb/chip_bind.sv
binds thetlul_assert
assertions to the IP to ensure TileLink interface protocol compliance. - Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
- assert prop 1:
- assert prop 2:
Building and running tests
DV simulations for top_earlgrey
are run with the dvsim
tool.
Please take a look at the link for detailed information on the usage, capabilities, features and known issues.
The basic UART transmit and receive test can be run with the following command:
$ ./util/dvsim/dvsim.py hw/top_earlgrey/dv/chip_sim_cfg.hjson -i chip_uart_tx_rx
For a list of available tests to run, please see the ‘Tests’ column in the testplan below.
Regressions
Sanity
SW access
Nightly
Testplan (RTL simulations)
Testpoints
Milestone | Name | Tests | Description | |||||||||||||||||||||||||||||||||||||||||||||
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V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | Verify transmission of data over the TX and RX port. SW test sends a known payload over the TX port. The testbench, at the same time sends a known payload over RX. On reception, both payloads are checked for integrity. SW validates the reception of TX watermark, RX watermark, and the TX empty interrupts. Choosing the max supported baud rate for the UART is sufficient. Verify each UART instance at the chip level independently. Verify there is no aliasing on all UART ports across the instances. | |||||||||||||||||||||||||||||||||||||||||||||
V1 | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx chip_sw_uart_tx_rx_idx1 chip_sw_uart_tx_rx_idx2 chip_sw_uart_tx_rx_idx3 | Verify the RX overflow interrupt. The testbench sends a random payload of size greater than the RX fifo size (32). The SW ignores the received the data to allow the RX overflow interrupt to assert. Verify each UART instance at the chip level independently. Verify there is no aliasing on all UART ports across the instances. | |||||||||||||||||||||||||||||||||||||||||||||
V1 | chip_sw_uart_rand_baudrate | chip_sw_uart_rand_baudrate | Verify UART transmission of data at various speeds. Randomly pick one of the UART instances and configure it to run with any of these baud rates - 9600bps, 115200bps, 230400bps, 128Kbps, 256Kbps, 1Mkbps, 1.5Mkbps. | |||||||||||||||||||||||||||||||||||||||||||||
V1 | chip_sw_uart_tx_rx_alt_clk_freq | chip_sw_uart_tx_rx_alt_clk_freq chip_sw_uart_tx_rx_alt_clk_freq_low_speed chip_sw_uart_tx_rx_alt_clk_fast_ip_clk | Verify the transmission of UART via using external clock as uart core clock. Extend from chip_sw_uart_rand_baudrate with following added settings.
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V1 | chip_sw_gpio_out | chip_sw_gpio | Verify GPIO outputs. SW test configures the GPIOs to be in the output mode. The test walks a 1 through the pins. The testbench checks the value for correctness and verifies that there is no aliasing between the pins. | |||||||||||||||||||||||||||||||||||||||||||||
V1 | chip_sw_gpio_in | chip_sw_gpio | Verify GPIO inputs. The SW test configures the GPIOs to be in input mode. The testbench walks a 1 through the pins. SW test ensures that the GPIO values read from the CSR is correct. | |||||||||||||||||||||||||||||||||||||||||||||
V1 | chip_sw_gpio_irq | chip_sw_gpio | Verify GPIO interrupts. The SW test configures the GPIOs to be in input mode and enables all of them to generate an interrupt. The testbench walks a 1 through the pins. SW test ensures that the interrupt corresponding to the right pin is seen. | |||||||||||||||||||||||||||||||||||||||||||||
V1 | chip_sw_example_test_from_rom_or_flash | chip_sw_example_flash chip_sw_example_rom | Run examples tests developed for each boot stage. Our test infrastructure defaults to running tests out flash, at the ROM_EXT stage, but also supports running tests in the ROM stage. We develop example tests to demonstrate these capabilities, and need to run them in DV to ensure the integrity of our infrastructure. | |||||||||||||||||||||||||||||||||||||||||||||
V1 | csr_hw_reset | chip_csr_hw_reset | Verify the reset values as indicated in the RAL specification.
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V1 | csr_rw | chip_csr_rw | Verify accessibility of CSRs as indicated in the RAL specification.
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V1 | csr_bit_bash | chip_csr_bit_bash | Verify no aliasing within individual bits of a CSR.
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V1 | csr_aliasing | chip_csr_aliasing | Verify no aliasing within the CSR address space.
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V1 | csr_mem_rw_with_rand_reset | chip_csr_mem_rw_with_rand_reset | Verify random reset during CSR/memory access.
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V1 | regwen_csr_and_corresponding_lockable_csr | chip_csr_rw chip_csr_aliasing | Verify regwen CSR and its corresponding lockable CSRs.
Note:
This is only applicable if the block contains regwen and locakable CSRs. | |||||||||||||||||||||||||||||||||||||||||||||
V1 | xbar_smoke | xbar_chip_smoke | Sequentially test each host to access any device | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_spi_device_tx_rx | chip_sw_spi_device_tx_rx | Verify the transmission of data on the chip's SPI device port in firmware mode with single mode.
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V2 | chip_sw_spi_device_flash_mode | Verify the SPI device in flash mode.
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V2 | chip_sw_spi_device_pass_through | Verify the pass through mode from an end-to-end perspective.
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V2 | chip_sw_spi_device_pass_through_filter | Verify the command filtering mechanism in passthrough mode.
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V2 | chip_sw_spi_device_pass_through_flash_model | Verify the command filtering mechanism in passthrough mode.
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V2 | chip_conn_spi_device_ast | Verify the connectivity between spi_device and AST on scanmode and mbist This could be done through the connectivity test with FPV | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_spi_device_pass_through_collision | Verify the collisions on driving spi_host is handled properly TODO, add detail testplan once we have a conclusion on #5134 | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_spi_host_tx_rx | Verify the transmission of data on the chip's SPI host port.
Verify all SPI host instances in the chip. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_i2c_host_tx_rx | Verify the transmission of data over the chip's I2C host interface.
Verify all instances of I2C in the chip. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_i2c_device_tx_rx | Verify the transmission of data over the chip's I2C device interface.
Verify all instances of I2C in the chip. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_usb_fs_tx_rx | Verify the transmission of single-ended data over the USB at full speed. As a part of this test, the enablement of USB pullup is also expected to be verified.
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V2 | chip_sw_usb_vbus | Verify that the USB device can detect the presence of VBUS from the USB host.
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V2 | chip_sw_usb_suspend | Verify that the USB device can detect the presence of VBUS from the USB host.
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V2 | chip_usb_sof | Verify that USB can detect SOF and respond with
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V2 | chip_usb_wake_debug | Verify that
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V2 | chip_usb_enumeration | Verify USB enumeration. Details are not clear.
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V2 | chip_sw_pin_mux | Verify the MIO muxing at input and output sides. SW programs MIO INSEL and OUTSEL CSRs to connect and verify each muxed source. At the moment, GPIOs are the only mux inputs. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_sleep_pin_mio_dio_val | Verify the MIO output values in deep sleep state. SW programs the MIO OUTSEL CSRs to to ensure that in deep sleep it randomly picks between tie-0, tie-1 or hi-Z for all muxed outputs coming from non-AON IPs. If an AON peripheral output is muxed, then that peripheral's output is selected to ensure in deep sleep the peripheral can continue its signaling even in deep sleep. The testbench verifies the correctness of the reflected values once the chip goes into deep sleep. This is replicated for DIO pins as well. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_sleep_pin_wake | Verify pin wake up from deep sleep state. Verify one of the 8 possible MIO or DIO pad inputs (randomly configured) can cause the chip to wake up from sleep state. Verifying wake on posedge is sufficient for the chip level integration testing. Upon wake up, SW reads the wake cause CSR to verify correctness. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_tap_strap_sampling | chip_tap_straps_dev chip_tap_straps_prod chip_tap_straps_rma | Verify tap accesses in different LC states. Verify pinmux can select the life_cycle, RISC-V, and DFT taps after reset. Verify that in TEST_UNLOCKED* and RMA states, pinmux can switch between the three TAPs without issuing reset. Verify in PROD state, only the LC tap can be selected. Verify in DEV state, only the LC tap and RISC-V taps can be selected. Verify DFT test mode straps are sampled and output to AST via top_earlgrey.dft_strap_test_o in TEST_UNLOCKED* and RMA states. Verify top_earlgrey.dft_strap_test_o is always 0 in the states other than TEST_UNLOCKED* and RMA, regardless of the value on DFT SW straps. | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_padctrl_attributes | Verify pad attribute settings for all MIO and DIO pads. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_pattgen_ios | Verify pattern generation to chip output pads.
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V2 | chip_sw_sleep_pwm_pulses | chip_sw_sleep_pwm_pulses | Verify PWM signaling to chip output pads during deep sleep.
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V2 | chip_sw_data_integrity | Verify the alert signaling mechanism due to data integrity violation. An automated SW test which performs the following for each IP:
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V2 | chip_jtag_csr_rw | chip_jtag_csr_rw | Verify accessibility of all the CSRs in the chip over JTAG.
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V2 | chip_jtag_mem_access | chip_jtag_mem_access | Verify accessibility of all the memories in the chip over JTAG. This test will target the following memories in the chip: sram_main, sram_ret, otbn i|dmem, ROM
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V2 | chip_rv_dm_cpu_debug_mem_not_accessable | Verify that the debug mem can't be accessed from the CPU while not in the debug mode. TODO, add stimulus and checks | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_rv_dm_perform_debug |
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V2 | chip_rv_dm_ndm_reset_req | chip_rv_dm_ndm_reset_req | Verify non-debug reset request initiated from RV_DM when the chip is awake.
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V2 | chip_rv_dm_ndm_reset_req_when_ibex_halted | Verify non-debug reset request initiated from RV_DM when ibex is in halted state.
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V2 | chip_rv_dm_access_after_wakeup | Verify RV_DM works after wakes up from sleep.
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V2 | chip_sw_rv_dm_jtag_tap_sel | Verify ability to select all available TAPs.
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V2 | chip_sw_rv_dm_lc_disabled | Verify that the debug capabilities are disabled in certain life cycle stages.
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V2 | chip_sw_timer | chip_sw_rv_timer_irq | Verify the timeout interrupt assertion.
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V2 | chip_sw_aon_timer_wakeup_irq | chip_sw_aon_timer_irq | Verify the AON timer wake up interrupt in normal operating state.
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V2 | chip_sw_aon_timer_sleep_wakeup | chip_sw_pwrmgr_smoketest | Verify that AON timer can wake up the chip from a deep sleep state.
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V2 | chip_conn_aon_timer_clks_resets | Verify that the correct clocks and resets are connected to the AON timer.
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V2 | chip_sw_aon_timer_wdog_bark_irq | chip_sw_aon_timer_irq | Verify the watchdog bark reception in normal state.
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V2 | chip_sw_aon_timer_wdog_lc_escalate | chip_sw_aon_timer_wdog_lc_escalate | Verify that the LC escalation signal disables the AON timer wdog.
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V2 | chip_sw_aon_timer_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | Verify the watchdog bite causing reset in the normal state.
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V2 | chip_sw_aon_timer_sleep_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | Verify the watchdog bite causing reset in sleep state.
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V2 | chip_sw_aon_timer_sleep_wdog_sleep_pause | chip_sw_aon_timer_sleep_wdog_sleep_pause | Verify that the wdog can be paused in sleep state.
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V2 | chip_sw_plic_all_irqs | chip_plic_all_irqs | Verify all interrupts from all peripherals aggregated at the PLIC. The automated SW test enables all interrupts at the PLIC to interrupt the core. It uses
the | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_plic_sw_irq | chip_sw_plic_sw_irq | Verify the SW interrupt to the CPU. Enable all peripheral interrupts at PLIC. Enable all types of interrupt at the CPU core. Write to the MSIP CSR to generate a SW interrupt to the CPU. Verify that the only interrupt that is seen is the SW interrupt. | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_plic_nmi_irq | Verify the NMI interrupt to the CPU and correctness of the cause. TBD if multiple NMI irqs are OR-ed into the CPU (example - NMI from alert handler and the watchdog bark), then map each test to this testpoint. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_clkmgr_idle_trans | chip_sw_aes_idle chip_sw_hmac_enc_idle chip_sw_kmac_idle chip_sw_otbn_randomness | Verify the ability to turn off the transactional clock via SW. Ensure that the clock to transactional units will be turned off after any activity completes in the transactional IP. Verify it is off via spinwait in hints_status CSR. Verify that turning off this clock does not affect the other derived clocks. | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_clkmgr_off_trans | chip_sw_clkmgr_off_aes_trans chip_sw_clkmgr_off_hmac_trans chip_sw_clkmgr_off_kmac_trans chip_sw_clkmgr_off_otbn_trans | Verify the turned off transactional units. Verify CSR accesses do not complete in units that are off. Using the watchdog timers, turn off a transactional unit's clock, issue a CSR access to that unit, verify a watchdog event results, and verify the rstmgr crash dump info records the CSR address. A stretch goal is to check the PC corresponds to the code performing the CSR access (stretch since it could be difficult to maintain this check). | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_clkmgr_off_peri | chip_sw_clkmgr_off_peri | Verify the ability to turn off the peripheral clock via SW. Verify CSR accesses do not complete in peripherals that are off. Using the watchdog timers, turn off a peripheral's clock, issue a CSR access to that peripheral, verify a watchdog event results, and verify the rstmgr crash dump info records the CSR address. | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_conn_clkmgr_div | chip_sw_clkmgr_external_clk_src_for_sw_fast chip_sw_clkmgr_external_clk_src_for_sw_slow chip_sw_clkmgr_external_clk_src_for_lc | Verify clk division logic is working correctly. The IP level checks the divided clocks via SVA, and these are also bound at chip level. Connectivity tests check peripherals are connected to the clock they expect. Use the clkmgr count measurement feature to verify clock division. | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_clkmgr_external_clk_src_for_lc | chip_sw_clkmgr_external_clk_src_for_lc | Verify the clkmgr requests ext clk src during certain LC states. On POR lc asserts lc_clk_byp_req on some LC states, and de-asserts it when lc_program completes. This also triggers divided clocks to step down. It may be best to verify this via SVA, unless we implement clock cycle counters. | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_clkmgr_external_clk_src_for_sw | chip_sw_clkmgr_external_clk_src_for_sw_fast chip_sw_clkmgr_external_clk_src_for_sw_slow | Verify SW causes the clkmgr requests ext clk src during certain LC states. In RMA and TEST_UNLOCKED lc states the external clock is enabled in response to
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V2 | chip_sw_clkmgr_jitter | chip_sw_clkmgr_jitter chip_sw_flash_ctrl_ops_jitter_en chip_sw_flash_ctrl_access_jitter_en chip_sw_otbn_ecdsa_op_irq_jitter_en chip_sw_aes_enc_jitter_en chip_sw_hmac_enc_jitter_en chip_sw_keymgr_key_derivation_jitter_en chip_sw_kmac_mode_kmac_jitter_en chip_sw_sram_ctrl_main_scrambled_access_jitter_en | Verify the clock jitter functionality. Enable clock jitter setting the clkmgr X-ref with various specific jitter enable tests. | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_clkmgr_deep_sleep_frequency | chip_sw_ast_clk_outputs | Verify the frequency measurement through deep sleep. Enable clock cycle counts. Put the chip in deep sleep. Upon wakeup reset the clock measurements should be off, but the recoverable fault status should not be cleared. | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_clkmgr_sleep_frequency | Verify the frequency measurement through shallow sleep. Enable clock cycle counts. Put the chip in shallow sleep with pwrmgr's CONTROL CSR randomly enabling clocks. Upon wakeup interrupt the clock measurements should be on, and the recoverable fault status may have faults for only the disabled clocks. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_clkmgr_reset_frequency | Verify the frequency measurement through reset. Enable clock cycle counts, configured to cause errors. Trigger a chip reset via SW. After reset the clock measurements should be off and the recoverable fault status should be cleared. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_clkmgr_escalation_reset | Verify the clock manager resets to a clean state after an escalation reset. Trigger an internal fault (measurement error timeout) and let it escalate to reset. Upon alert escalation reset, the internal status should be clear and clkmgr should not attempt to send out more alerts. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_pwrmgr_external_full_reset | chip_sw_pwrmgr_full_aon_reset | Verify the cold boot sequence by wiggling of chip's This ensures that both FSMs are properly reset on the POR signal. The check is that
the processor ends up running. Also verify, the rstmgr records POR in | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_pwrmgr_normal_sleep_all_wake_ups | chip_sw_pwrmgr_normal_sleep_all_wake_ups | Verify that the chip can go into normal sleep state and be woken up by ALL wake up sources. This verifies ALL wake up sources. This also verifies that the pwrmgr sequencing is
working correctly as expected. X-ref'ed with all individual IP tests. For each wakeup
source clear and enable | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_pwrmgr_sleep_all_reset_reqs | chip_sw_aon_timer_wdog_bite_reset | Verify that the chip can go into normal sleep state and be reset by ALL reset req sources. This verifies ALL reset sources. This also verifies that the pwrmgr sequencing is
working correctly as expected. X-ref'ed with all individual IP tests. For each reset
source, enable the source and bring the chip to low power, issue a reset, and verify the
rstmgr's | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_pwrmgr_deep_sleep_all_wake_ups | chip_sw_pwrmgr_deep_sleep_all_wake_ups | Verify that the chip can go into deep sleep state and be woken up by ALL wake up sources. This verifies ALL wake up sources. This also verifies that the pwrmgr sequencing is
working correctly as expected. X-ref'ed with all individual IP tests. Similar to
chip_pwrmgr_sleep_all_wake_ups, except | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | Verify that the chip can go into deep sleep state and be reset up by ALL reset req sources. This verifies ALL reset sources.
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V2 | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | Verify that the chip can go into normal sleep state and be reset up by ALL reset req sources. This verifies ALL reset sources.
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_pwrmgr_wdog_reset | chip_sw_pwrmgr_wdog_reset | Verify that the chip can be reset by watchdog timer reset source. This verifies watchdog timer reset source. This also verifies that the pwrmgr sequencing is working correctly as expected. X-ref'ed with all individual IP tests. Similar to chip_pwrmgr_sleep_all_reset_reqs, except the chip is not put in low power mode. | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_pwrmgr_aon_power_glitch_reset | chip_sw_pwrmgr_full_aon_reset | Verify the cold boot sequence through an AON power glitch. Pulsing the AST vcaon_supp_i input causes an AON power glitch which becomes a POR.
This ensures that both FSMs are properly reset on the POR signal. The check is that
the processor ends up running. Also verify, the rstmgr records POR in | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_pwrmgr_main_power_glitch_reset | chip_sw_pwrmgr_main_power_glitch_reset | Verify the effect of a glitch in main power rail. The vcmain_supp_i AST input is forced to drop once the test is running. This triggers a MainPwr reset request, which is checked reading the reset_info CSR when the test restarts and the POR bit is not set. | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | Verify the effect of a glitch in main power rail in deep sleep. The vcmain_supp_i AST input is forced to drop right after putting the chip in deep sleep. This triggers a MainPwr reset request, which is checked reading the reset_info CSR when the test restarts and the POR bit is not set. Note: the glitch has to be sent in a very narrow window:
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_pwrmgr_sleep_power_glitch_reset | chip_sw_pwrmgr_sleep_power_glitch_reset | Verify the effect of a glitch in main power rail in shallow sleep. The vcmain_supp_i AST input is forced to drop after putting the chip in shallow sleep. This triggers a MainPwr reset request, which is checked reading the reset_info CSR when the test restarts and the POR bit is not set. | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_pwrmgr_random_sleep_all_reset_reqs | chip_sw_pwrmgr_random_sleep_all_reset_reqs | Verify that this chip can be reset by All available reset sources.
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_pwrmgr_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | Verify the effect of a sysrst_ctrl output in main power rail.
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_pwrmgr_b2b_sleep_reset_req | chip_sw_pwrmgr_b2b_sleep_reset_req | Verify that the pwrmgr sequences sleep_req and reset req coming in almost at the same time, one after the other. Use POR_N PAD to trigger reset. | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_pwrmgr_debug_sleep | Verify low power entry is prevented when the chip is in "debuggable" state. This is an open issue: https://github.com/lowRISC/opentitan/issues/7215 | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_pwrmgr_sleep_disabled | Verify that the chip does not go to sleep on WFI when low power hint is 0. This calls WFI with low_power_hint disabled and pwrmgr interrupts enabled, and fails if the pwrmgr ISR is called. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_pwrmgr_escalation_reset | Verify the power manager resets to a clean state after an internal fault causes the system to escalate to reset. Upon alert escalation reset, the internal status should be clear and the pwrmgr should not attempt to send out more alerts. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_rstmgr_non_sys_reset_info | chip_sw_pwrmgr_smoketest | Verify the Generate the 5 types of reset at This should also check the reset's destination IP to make sure some reset side-effect
is present. Setting some | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_rstmgr_sys_reset_info | Verify the Generate reset triggered by This should also check the reset's destination IP to make sure some reset side-effect
is present. Setting some | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_rstmgr_cpu_info | chip_sw_rstmgr_cpu_info | Verify the expected values from the For some software induced resets we can predict the expected contents of | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_rstmgr_sw_req_reset | chip_sw_rstmgr_sw_req | Verify software requested device reset. Generate a reset request by directly writing the | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_rstmgr_alert_info | chip_sw_rstmgr_alert_info | Verify the expected values from the Various alerts can be created, for example, timeouts, and integrity errors, and at
least part of the | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_rstmgr_sw_rst | chip_sw_rstmgr_sw_rst | Verify
Notice the two | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_rstmgr_escalation_reset | Verify the reset manager resets to a clean state after an internal fault causes the system to escalate to reset. Upon alert escalation reset, the internal status should be clear and the rstmgr should not attempt to send out more alerts. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_alert_handler_alerts | chip_sw_alert_test | Verify all alerts coming into the alert_handler. An automated SW test, which does the following (applies to all alerts in all IPs):
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_alert_handler_escalations | Verify all alert escalation paths. Verify all escalation paths triggered by an alert.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_alert_handler_irqs | chip_plic_all_irqs | Verify all classes of alert handler interrupts to the CPU. X-ref'ed with the automated PLIC test. | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_alert_handler_entropy | Verify the alert handler entropy input to ensure pseudo-random ping timer.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_alert_handler_crashdump | Verify the alert handler crashdump signal. When the chip resets due to alert escalating to cause the chip to reset, verify the reset cause to verify the alert crashdump. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_alert_handler_ping_timeout | chip_sw_alert_handler_ping_timeout | Verify the alert senders' ping timeout. Set alert_handler's ping timeout cycle to 2 and enable alert_senders. Verify that
alert_handler detects the ping timeout and reflects it on the | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_alert_handler_lpg_sleep_mode_alerts | Verify alert_handler can preserve alerts during low_power mode.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_alert_handler_lpg_sleep_mode_pings | Verify alert_handler's ping mechanism works correctly during sleep and wake up. There are two scenarios to check:
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_alert_handler_lpg_clock_off | Verify alert_handler's works correctly when sender clock is turned off.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_alert_handler_lpg_reset_toggle | Verify alert_handler's works correctly when sender reset is toggled.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_alert_handler_reverse_ping_in_deep_sleep | Verify escalation reverse ping timer disabled in sleep mode. Check that escalation receivers located inside always-on blocks do not auto-escalate due to the reverse ping feature while the system is in deep sleep. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_lc_ctrl_alert_handler_escalation | Verify that the escalation signals from the alert handler are connected to LC ctrl.
X-ref'ed with chip_lc_ctrl_broadcast test, which verifies the connectivity of the LC decoded outputs to other IPs. X-ref'ed with alert_handler's escalation test. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_lc_ctrl_jtag_access | chip_tap_straps_dev chip_tap_straps_prod chip_tap_straps_rma | Verify enable to access LC ctrl via JTAG. Using the JTAG agent, write and read LC ctrl CSRs, verify the read value for correctness. | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_lc_ctrl_jtag_trst | Verify the JTAG test reset input connection to LC ctrl. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_lc_ctrl_otp_hw_cfg | chip_sw_lc_ctrl_otp_hw_cfg | Verify the device_ID and ID_state CSRs
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_lc_ctrl_init | chip_sw_lc_ctrl_transition | Verify the LC ctrl initialization on power up. Verify that the chip powers up correctly on POR.
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_lc_ctrl_transitions | chip_sw_lc_ctrl_transition | Verify the LC ctrl can transit from one state to another valid state with the correct tokens.
X-ref'ed chip_sw_otp_ctrl_program. | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_lc_ctrl_kmac_req | chip_sw_lc_ctrl_transition | Verify the token requested from KMAC.
X-ref'ed with chip_kmac_lc_req. | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_lc_ctrl_kmac_reset | Verify the effect of putting the KMAC logic in reset during LC state transition.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_lc_ctrl_key_div | Verify the keymgr div output to keymgr.
X-ref'ed with chip_keymgr_lc_key_div_o. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_lc_ctrl_broadcast | Verify broadcast signals from lc_ctrl.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_conn_lc_ctrl_scanmode | Verify the connectivity of scanmode to LC ctrl. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_conn_ctrl_scanmode_reset | Verify the connectivity of scanmode reset to LC ctrl. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_sysrst_ctrl_inputs | chip_sw_sysrst_ctrl_inputs | Verify that the SYSRST ctrl input pin values can be read.
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_sysrst_ctrl_outputs | Verify that the SYSRST ctrl output pin values can be set.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_sysrst_ctrl_in_irq | Verify the SYSRST ctrl can detect an input combination to signal an interrupt.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_sysrst_ctrl_sleep_wakeup | chip_sw_sysrst_ctrl_reset | Verify the SYSRST ctrl can wake up the chip from deep sleep.
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_sysrst_ctrl_reset | chip_sw_sysrst_ctrl_reset | Verify the SYSRST ctrl can reset the chip from normal state.
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_sysrst_ctrl_sleep_reset | chip_sw_sysrst_ctrl_reset | Verify the SYSRST ctrl can reset the chip from deep sleep.
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_sysrst_ctrl_ec_rst_l | Verify that the ec_rst_l stays asserted on power-on-reset until SW can control it.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_sysrst_ctrl_flash_wp_l | Verify that the flash_wp_l stays asserted on power-on-reset until SW can control it.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_sysrst_ctrl_ulp_z3_wakeup | Verify the z3_wakeup signaling.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_adc_ctrl_debug_cable_irq | Verify that the ADC correctly detects the voltage level programmed for each channel.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | Verify that in deep sleep, ADC ctrl can signal the ADC within the AST to power down.
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_aes_enc | chip_sw_aes_enc chip_sw_aes_enc_jitter_en | Verify the AES operation. Write a 32-byte key and a 16-byte plain text to the AES registers and trigger the AES computation to start. Wait for the AES operation to complete by polling the status register. Check the digest registers for correctness against the expected digest value. | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_aes_entropy | chip_sw_aes_entropy | Verify the AES entropy input used by the internal PRNGs.
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_aes_idle | chip_sw_aes_idle | Verify AES idle signaling to clkmgr.
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_aes_sideload | Verify the AES sideload mechanism. Details TBD, design updates pending. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_hmac_enc | chip_sw_hmac_enc_irq chip_sw_hmac_enc chip_sw_hmac_enc_jitter_en | Verify HMAC operation. SW test verifies an HMAC operation with a known key, plain text and digest (pick one of the NIST vectors). SW test verifies the digest against the pre-computed value. Verify the HMAC done and FIFO empty interrupts as a part of this test. | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_hmac_idle | chip_sw_hmac_idle | Verify the HMAC clk idle signal to clkmgr.
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_kmac_enc | chip_sw_kmac_mode_cshake chip_sw_kmac_mode_kmac chip_sw_kmac_mode_kmac_jitter_en | Verify the SHA3 operation. SW test verifies SHA3 operation with a known key, plain text and digest (pick one of the NIST vectors). SW validates the reception of kmac done and fifo empty interrupts. | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_kmac_app_keymgr | Verify the keymgr interface to KMAC.
X-ref'ed with keymgr test. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_kmac_app_lc | chip_sw_lc_ctrl_transition | Verify the LC interface to KMAC.
X-ref'ed with LC_CTRL test/env. | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_kmac_app_rom | chip_sw_kmac_app_rom | Verify the ROM interface to KMAC.
X-ref'ed with ROM_CTRL test/env. | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_kmac_idle | chip_sw_kmac_idle | Verify the KMAC idle signaling to clkmgr.
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_entropy_src_ast_rng_req | chip_sw_entropy_src_ast_rgn_req | Verify the RNG req to ast.
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_entropy_src_ast_fips | Verify the connectivity of rng_fips_o feedback signal to RNG. Details TBD. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_entropy_src_csrng | Verify the transfer of entropy bits to CSRNG. Verify the entropy valid interrupt. At the CSRNG, validate the reception of entropy req interrupt. Details TBD. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_entropy_src_cs_aes_halt | Verify the aes halt handshake with CSRNG. Details TBD. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_entropy_src_fuse_en_fw_read | Verify the fuse input entropy_src.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_entropy_src_known_answer_tests | chip_sw_entropy_src_kat_test | Verify our ability to run known-answer tests in SW.
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_csrng_edn_cmd | Verify incoming command interface from EDN.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_csrng_fuse_en_sw_app_read | Verify the fuse input to CSRNG.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_csrng_lc_hw_debug_en | Verify the effect of LC HW debug enable on CSRNG. TODO: This is pending SCA security review and might be removed. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_csrng_known_answer_tests | chip_sw_csrng_kat_test | Verify our ability to run known-answer tests in SW.
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_edn_entropy_reqs | Verify the entropy requests from all peripherals. Verify that there are no misconnects between each peripheral requesting entropy. TODO: system level scenario: have all entropy sources request entropy in the same test one after to show boot to post boot load, cycling all entropy blocks off and on again. Ensure there are no deadlocks and everything works as expected. X'ref'ed with each IP test that requsts entropy from EDN. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_keymgr_key_derivation | chip_sw_keymgr_key_derivation chip_sw_keymgr_key_derivation_jitter_en | Verify the keymgr advances to all states and generate identity / SW output.
X-ref'ed with kmac test. | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_keymgr_sideload_kmac | Verify the keymgr sideload interface to KMAC, similar to
X-ref'ed with chip_kmac_app_keymgr test. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_keymgr_sideload_aes | Verify the keymgr sideload interface to AES. Same as | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_keymgr_sideload_otbn | Verify the keymgr sideload interface to OTBN. Load OTBN binary image, the rest is similar to | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_otbn_op | chip_sw_otbn_ecdsa_op_irq chip_sw_otbn_ecdsa_op_irq_jitter_en | Verify an OTBN operation.
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_otbn_rnd_entropy | chip_sw_otbn_randomness | Verify OTBN can fetch RND numbers from the entropy src.
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_otbn_urnd_entropy | chip_sw_otbn_randomness | Verify OTBN can fetch URND numbers from the entropy src.
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_otbn_idle | chip_sw_otbn_randomness | Verify the OTBN idle signal to clkmgr.
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_conn_otbn_ast_ram_cfg | Verify that the ram_cfg signal from AST is connected to OTBN.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_otbn_mem_scramble | chip_sw_otbn_mem_scramble | Verify the OTBN can receive keys from the OTP to scramble the OTBN imem and dmem.
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_rom_access | chip_sw_rom_ctrl_integrity_check | Verify that the CPU can access the rom contents.
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_conn_rom_ctrl_ast_rom_cfg | Verify that the rom_cfg signal from AST is connected to ROM ctrl.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check | Verify that the ROM ctrl performs the integrity check of the ROM on power up.
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_sram_scrambled_access | chip_sw_sram_ctrl_ret_scrambled_access chip_sw_sram_ctrl_main_scrambled_access chip_sw_sram_ctrl_main_scrambled_access_jitter_en | Verify scrambled memory accesses to both main and retention SRAMs.
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_sleep_sram_ret_contents | chip_sw_sleep_sram_ret_contents | Verify that the data within the retention SRAM survives low power entry-exit. Ensure that the data within the retention SRAM survives ALL low power entry-exit variations. TODO: how to deal with the scramble keys on low power exit? | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_sram_execution | chip_sw_sram_ctrl_execution_main | Verify that CPU can fetch instructions from SRAM if enabled.
The following table indicates in which of these scenarios should the instruction execution be enabled, for both, main and the retention SRAM instances.
For the retention SRAM, instruction fetch is completely disabled via design parameter. | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_sram_lc_escalation | Verify the LC escalation path to the SRAMs.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_otp_ctrl_init | chip_sw_lc_ctrl_transition | Verify the OTP ctrl initialization on chip power up. Verify that the chip powers up correctly on POR.
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_otp_ctrl_keys | Verify the proliferation of keys to security peripherals.
X-ref'ed with IP tests that consume these signals. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_otp_ctrl_entropy | Verify the entropy interface from OTP ctrl to EDN. This is X-ref'ed with the chip_otp_ctrl_keys test, which needs to handshake with the EDN to receive some entropy bits before the keys for SRAM ctrl and OTBN are computed. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_otp_ctrl_edn_reset | Verify the effect of putting the EDN domain in reset on OTP ctrl. Verify that the computed nonce for SRAM is reset? Verify all entropy data used for various things are reset. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_otp_ctrl_program | chip_sw_lc_ctrl_transition | Verify the program request from lc_ctrl.
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_otp_ctrl_program_error | Verify the otp program error.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_otp_ctrl_hw_cfg | chip_sw_lc_ctrl_otp_hw_cfg | Verify the correctness of otp_hw_cfg bus in all peripherals that receive it. Preload the OTP ctrl's Xref'ed with corresponding IP tests that receive these bits. | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_otp_ctrl_lc_signals | Verify the broadcast signals from LC ctrl.
X-ref'ed with chip_lc_ctrl_broadcast test, which verifies the connectivity of the LC decoded outputs to other IPs. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_otp_ctrl_ast | Verify the power sequencing signals to AST, as well as the alert. Details TBD. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_conn_otp_ctrl_external_voltage | Verify the connectivity of the external voltage signal to OTP ctrl. Details TBD. TODO; This signal is not connected in the design yet. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_conn_otp_ctrl_scan | Verify the connectivity of the scan signals to OTP ctrl. Details TBD. TODO; This signal is not connected in the design yet. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_flash_init | chip_sw_flash_init | Verify that flash initialization routine works correctly.
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_flash_host_access | chip_sw_flash_ctrl_access chip_sw_flash_ctrl_access_jitter_en | Verify that the flash memory contents can be read by the CPU. Nothing extra to do here - most SW based tests fetch code from flash. | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_flash_ctrl_ops | chip_sw_flash_ctrl_ops chip_sw_flash_ctrl_ops_jitter_en | Verify the SW can initiate flash operations via the controller. Verify that the CPU can read / program and erase the flash mem. Pick an operation on all data and info partitions. Erase both, bank and page. SW validates the reception of prog empty, prog level, rd full, rd level and op done interrupts. | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_flash_rma_unlocked | chip_sw_flash_rma_unlocked | Verify the flash memory contents can be accessed after in RMA unlock.
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_conn_flash_jtag | Verify that the JTAG interface for the closed source flash macro is connected from chip IOs. In open source, this JTAG interface is null-terminated, so we can only verify this through a connectivity test. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_flash_scramble | chip_sw_flash_init | Verify flash scrambling via the controller.
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_flash_idle_low_power | chip_sw_flash_ctrl_idle_low_power | Verify flash_idle signaling to pwrmgr.
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_flash_keymgr_seeds | Verify the creator and owner seeds are read on flash init provided lc_hw_seed_rd_en is set. X-ref'ed with keymgr test. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_flash_lc_creator_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | Verify the lc_creator_seed_sw_rw_en signal from LC ctrl.
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_flash_creator_seed_wipe_on_rma | chip_sw_flash_rma_unlocked | Verify that the creator seed is wiped by the flash ctrl on RMA entry. | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_flash_lc_owner_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | Verify the lc_owner_seed_sw_rw_en signal from LC ctrl.
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_flash_lc_iso_part_sw_rd_en | chip_sw_flash_ctrl_lc_rw_en | Verify the lc_iso_part_sw_rd_en signal from LC ctrl.
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_flash_lc_iso_part_sw_wr_en | chip_sw_flash_ctrl_lc_rw_en | Verify the lc_creator_seed_sw_wr_en signal from LC ctrl.
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_flash_lc_seed_hw_rd_en | chip_sw_flash_ctrl_lc_rw_en | Verify the lc_seed_hw_rd_en signal from LC ctrl.
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_flash_lc_escalate_en | Verify the lc_escalate_en signal from LC ctrl.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_flash_prim_tl_access | Verify that the SW can read / write the dummy memory in flash phy.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_conn_flash_ast | Verify the connectivity of AST / top level signals.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_flash_ctrl_clock_freqs | chip_sw_flash_ctrl_clock_freqs | Verify flash program and erase operations over the ctrl over a range of clock freqs.
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_conn_flash_lc_nvm_debug_en | Verify that the lc_nvm_debug_en signal from LC ctrl is connected to the flash ctrl.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_ast_clk_outputs | chip_sw_ast_clk_outputs | Verify that the AST generates the 4 clocks when requested by the clkmgr. Verify the clock frequencies are reasonably accurate. Bring the chip to deep sleep, and verify that upon wakeup reset the clock counters are turned off, measure ctrl regwen is enabled, and errors are not cleared. | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_ast_clk_rst_inputs | Verify the clk and rst inputs to AST (from Details TBD. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_ast_sys_clk_jitter | Verify that the AST sys clk jitter control. Details TBD. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_ast_usb_clk_calib | Verify the USB clk calibration signaling. Details TBD. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_ast_alerts | chip_sw_sensor_ctrl_alert | Verify the alerts from AST aggregating into the sensor_ctrl. X-ref'ed with | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_sensor_ctrl_ast_alerts | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup chip_sw_sensor_ctrl_alert | Verify the alerts from AST aggregating into the sensor_ctrl. Check that AST events can be triggered from sensor_ctrl and that the resulting AST outputs are observed in both sensor_ctrl and the alert_handler. For the alert handler case, make sure to test each alert configured as either recoverable or fatal. | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_sensor_ctrl_ast_status | chip_sw_sensor_ctrl_status | Verify the io power ok status from AST. Check that when the IO POK status changes, an interrupt is triggered from sensor_ctrl. After triggering, the IO status can be read from a sensor_ctrl register. | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | Verify the sensor control is able to wake the device from sleep mode when an alert event is triggered from AST. X-ref'ed chip_sw_pwrmgr_sleep_all_wake_ups. | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_rv_core_ibex_rnd | Verify the functionality of the random number generation CSRs.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_rv_core_ibex_address_translation | Verify the simple address translation functionality.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_rv_core_ibex_fault_dump | Verify the functionality of the ibex fault dump.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_rv_core_ibex_double_fault | Verify the functionality of the ibex double fault dump.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_smoketest | chip_sw_aes_smoketest chip_sw_aon_timer_smoketest chip_sw_clkmgr_smoketest chip_sw_csrng_smoketest chip_sw_entropy_src_smoketest chip_sw_gpio_smoketest chip_sw_hmac_smoketest chip_sw_kmac_smoketest chip_sw_otbn_smoketest chip_sw_otp_ctrl_smoketest chip_sw_rv_plic_smoketest chip_sw_pwrmgr_smoketest chip_sw_rv_timer_smoketest chip_sw_rstmgr_smoketest chip_sw_sram_ctrl_smoketest chip_sw_uart_smoketest | Run smoke tests developed for each IP. The smoke tests are developed by the SW team to test each IP is alive, and can be actuated by the DIF. We need to ensure that they work in DV as well. | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_signed | chip_sw_uart_smoketest_signed | Run some chip-level tests with mask ROM. In addition to mask ROM E2E tests, we select at least one (or a few) tests defined in this file to sign, and run via mask ROM instead of test ROM. We need to ensure our test infrastructure and mask ROM can boot and run one (or a few) of the same tests our test ROM can. | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_coremark | chip_sw_coremark | Run the coremark benchmark on the full chip. | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_boot | chip_sw_uart_tx_rx_bootstrap | Verify the full flash image download with bootstrap signal set.
Note: This flow will be replaced by using spi_device flash mode. For detail, refer to chip_spi_device_flash_mode | |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_secure_boot | Verify the secure boot flow. Details TBD. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_lc_walkthrough | chip_sw_lc_walkthrough_dev chip_sw_lc_walkthrough_prod chip_sw_lc_walkthrough_prodend chip_sw_lc_walkthrough_rma chip_sw_lc_walkthrough_testunlocks | Walk through the life cycle stages from RAW state and reseting the chip each time.
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_device_ownership | Walk through device ownership stages and flows. Details TBD. | ||||||||||||||||||||||||||||||||||||||||||||||
V2 | chip_sw_sram_nmi_wipe | Verify SRAM behavior during an NMI escalation.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | tl_d_oob_addr_access | chip_tl_errors | Access out of bounds address and verify correctness of response / behavior | |||||||||||||||||||||||||||||||||||||||||||||
V2 | tl_d_illegal_access | chip_tl_errors | Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the [TLUL spec]({{< relref "hw/ip/tlul/doc/_index.md#explicit-error-cases" >}})
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | tl_d_outstanding_access | chip_csr_hw_reset chip_csr_rw chip_csr_aliasing chip_same_csr_outstanding | Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address. | |||||||||||||||||||||||||||||||||||||||||||||
V2 | tl_d_partial_access | chip_csr_hw_reset chip_csr_rw chip_csr_aliasing chip_same_csr_outstanding | Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields. | |||||||||||||||||||||||||||||||||||||||||||||
V2 | xbar_base_random_sequence | xbar_chip_random | Enable all hosts to randomly send transactions to any device | |||||||||||||||||||||||||||||||||||||||||||||
V2 | xbar_random_delay | xbar_chip_smoke_zero_delays xbar_chip_smoke_large_delays xbar_chip_smoke_slow_rsp xbar_chip_random_zero_delays xbar_chip_random_large_delays xbar_chip_random_slow_rsp | Control delays through plusargs to create tests for below types of delay
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | xbar_unmapped_address | xbar_chip_unmapped_addr xbar_chip_error_and_unmapped_addr |
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | xbar_error_cases | xbar_chip_error_random xbar_chip_error_and_unmapped_addr |
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | xbar_all_access_same_device | xbar_chip_access_same_device xbar_chip_access_same_device_slow_rsp |
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | xbar_all_hosts_use_same_source_id | xbar_chip_same_source | Test all hosts use same ID at the same same | |||||||||||||||||||||||||||||||||||||||||||||
V2 | xbar_stress_all | xbar_chip_stress_all xbar_chip_stress_all_with_error |
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | xbar_stress_with_reset | xbar_chip_stress_all_with_rand_reset xbar_chip_stress_all_with_reset_error |
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | mask_rom_functests | mask_rom_keymgr_functest | Run functests developed for mask ROM. Functests test mask ROM components (e.g., drivers, libraries, etc.) work as intended on-chip. However, unlike when these components are embedded in the mask ROM, functests are linked with the OTTF, and run out of flash. Additionally, unlike the mask ROM E2E tests, functests are booted by the test ROM. | |||||||||||||||||||||||||||||||||||||||||||||
V2 | mask_rom_e2e_bootup_no_rom_ext | Verify device fails to boot with no ROM_EXT.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | mask_rom_e2e_bootup_success | Verify device boots with a good ROM_EXT.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | mask_rom_e2e_bootup_bad_rom_ext_signature | Verify device fails to boot with an improperly-signed ROM_EXT.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | mask_rom_e2e_bootup_bad_manifest_usage_constraint | Verify device fails to boot with an invalid manifest usage constraints.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | mask_rom_e2e_bootup_rom_ext_invalidated_key | Verify device fails to boot with a ROM_EXT signed with an invalidated key.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | mask_rom_e2e_bootup_bad_rom_ext_version | Verify device fails to boot with a bad minimum version.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | mask_rom_e2e_bootstrap_success | Verify device enters bootstrap mode when strapping pins are set correctly.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | mask_rom_e2e_bootstrap_bad_pin_config | Verify the device does not enter bootstrap mode when strapping pins are set incorrectly.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | mask_rom_e2e_bootstrap_disabled | Verify device does not enter bootstrap mode when strapping pins are set correctly, but bootstrap is disabled in the OTP.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | mask_rom_e2e_bootstrap_config | Verify that JEDEC ID and SFDP are configured.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | mask_rom_e2e_bootstrap_phase1_reset_op | Verify that phase 1 of bootstrap handles RESET ops correctly.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | mask_rom_e2e_bootstrap_phase1_read_op | Verify that phase 1 of bootstrap handles READ ops correctly.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | mask_rom_e2e_bootstrap_phase1_page_program_op | Verify that phase 1 of bootstrap handles PAGE_PROGRAM ops correctly.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | mask_rom_e2e_bootstrap_phase1_erase_op | Verify that phase 1 of bootstrap handles ERASE ops correctly.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | mask_rom_e2e_bootstrap_phase2_reset_op | Verify that phase 2 of bootstrap handles RESET ops correctly.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | mask_rom_e2e_phase2_page_program_op | Verify that phase 2 of bootstrap correctly handles the PAGE_PROGRAM opcode.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | mask_rom_e2e_phase2_erase_op | Verify that phase 2 of bootstrap correctly handles the ERASE opcode.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | mask_rom_e2e_phase2_read_op | Verify that phase 2 of bootstrap correctly handles the READ opcode.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | mask_rom_e2e_startup_ast_main_sram_init | Verify that the AST and main SRAM are initialized correctly after POR. For each lifecycle state, perform the following:
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | mask_rom_e2e_startup_retention_sram_init | Verify that the retention SRAM is initialized correctly after POR.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | mask_rom_e2e_startup_retention_sram_saved | Verify that retention SRAM saves data across low-power entry/exit.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | mask_rom_e2e_startup_retention_sram_wiped | Verify that retention SRAM is wiped after a POR.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | mask_rom_e2e_shutdown_boot_failure | Verify that all boot failure cases enter shutdown.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | mask_rom_e2e_shutdown_alert_configuration | Verify that alert-handler is configured correctly.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | mask_rom_e2e_shutdown_mask_rom_alert_shutdown | Verify that alerts during Mask ROM execution lead to shutdown.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | mask_rom_e2e_shutdown_interrupts | Verify that interrupts lead to shutdown.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | mask_rom_e2e_upgradable | Verify that new firmware allows for upgrades.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | mask_rom_e2e_upgrade_min_sec_version | Verify that Mask ROM checks minimum security version before booting.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | mask_rom_e2e_upgrade_power_loss | Verify that losing power during a ROM_EXT upgrade does not brick the chip.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | mask_rom_rv_dm_perform_debug | Verify that Ibex enters debug mode when triggered through JTAG This test must be run with mask ROM. Mask ROM is responsible for enabling debug ROM access and must be used to ensure the epmp configurations are done correctly.
| ||||||||||||||||||||||||||||||||||||||||||||||
V2 | aon_timer_rst | aon_timer_rst | Verify rstmgr's resets_o is connected to aon_timer's reset port. | |||||||||||||||||||||||||||||||||||||||||||||
V2 | aon_timer_rst_aon | aon_timer_rst_aon | Verify rstmgr's resets_o is connected to aon_timer's aon-reset port. | |||||||||||||||||||||||||||||||||||||||||||||
V2 | ast_dft_ram_2p_cfg | ast_dft_spi_device_ram_2p_cfg ast_dft_usbdev_ram_2p_cfg | Verify ast model's dual port configuration bits are connected to the dual port RAMs in the following blocks:
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | ast_dft_ram_1p_cfg | ast_dft_otbn_imem_ram_1p_cfg ast_dft_otbn_dmem_ram_1p_cfg ast_dft_rv_core_ibex_tag0_ram_1p_cfg ast_dft_rv_core_ibex_tag1_ram_1p_cfg ast_dft_rv_core_ibex_data0_ram_1p_cfg ast_dft_rv_core_ibex_data1_ram_1p_cfg ast_dft_sram_main_ram_1p_cfg ast_dft_sram_ret_ram_1p_cfg ast_dft_rom_cfg | Verify ast model's single port configuration bits are connected to the single port RAMs in the following blocks:
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | ast_sys_clk_clkmgr | ast_sys_clk_clkmgr | Verify ast model's | |||||||||||||||||||||||||||||||||||||||||||||
V2 | ast_io_clk_clkmgr | ast_io_clk_clkmgr | Verify ast model's | |||||||||||||||||||||||||||||||||||||||||||||
V2 | ast_usb_clk_clkmgr | ast_usb_clk_clkmgr | Verify ast model's | |||||||||||||||||||||||||||||||||||||||||||||
V2 | ast_aon_clk_clkmgr | ast_aon_clk_clkmgr | Verify ast model's | |||||||||||||||||||||||||||||||||||||||||||||
V2 | clkmgr_jitter_ast | clkmgr_jitter_ast | Verify clkmgr's jitter enable is connected to ast. | |||||||||||||||||||||||||||||||||||||||||||||
V2 | clkmgr_idle | clkmgr_idle0 clkmgr_idle1 clkmgr_idle2 clkmgr_idle3 | Verify clkmgr's
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | clkmgr_clk_io_div4_infra | clkmgr_infra_clk_flash_ctrl_clk clkmgr_infra_clk_xbar_main_fixed_clk clkmgr_infra_clk_xbar_peri_peri_clk clkmgr_infra_clk_sram_ctrl_main_otp_clk clkmgr_infra_clk_sram_ctrl_ret_clk clkmgr_infra_clk_sram_ctrl_ret_otp_clk clkmgr_infra_clk_sysrst_ctrl_clk | Verify clkmgr's
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | clkmgr_clk_main_infra | clkmgr_infra_clk_flash_ctrl_clk clkmgr_infra_clk_rv_dm_clk clkmgr_infra_clk_rom_clk clkmgr_infra_clk_rv_core_ibex_clk clkmgr_infra_clk_rv_core_ibex_edn_clk clkmgr_infra_clk_sram_ctrl_main_clk clkmgr_infra_clk_xbar_main_main_clk | Verify clkmgr's
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | clkmgr_clk_aon_infra | infra_clk_sysrst_ctrl_aon_clk | Verify clkmgr's
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | clkmgr_clk_io_infra | clkmgr_infra_clk_xbar_main_spi_host0_clk | Verify clkmgr's
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | clkmgr_clk_io_div2_infra | clkmgr_infra_clk_xbar_main_spi_host1_clk | Verify clkmgr's
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | clkmgr_clk_io_div4_peri | clkmgr_peri_clk_adc_ctrl_aon_clk clkmgr_peri_clk_gpio_clk clkmgr_peri_clk_spi_device_clk clkmgr_peri_clk_i2c0_clk clkmgr_peri_clk_i2c1_clk clkmgr_peri_clk_i2c2_clk clkmgr_peri_clk_pattgen_clk clkmgr_peri_clk_uart0_clk clkmgr_peri_clk_uart1_clk clkmgr_peri_clk_uart2_clk clkmgr_peri_clk_uart3_clk clkmgr_peri_clk_usbdev_clk | Verify clkmgr's
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | clkmgr_clk_io_div2_peri | clkmgr_peri_clk_spi_device_scan_clk clkmgr_peri_clk_spi_host1_clk | Verify clkmgr's
| |||||||||||||||||||||||||||||||||||||||||||||
V2 | clkmgr_clk_io_peri | clkmgr_peri_clk_spi_host0_clk | Verify clkmgr's
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V2 | clkmgr_clk_usb_peri | clkmgr_peri_clk_usbdev_usb_clk | Verify clkmgr's | |||||||||||||||||||||||||||||||||||||||||||||
V2 | clkmgr_clk_aon_peri | clkmgr_peri_clk_adc_ctrl_aon_clk clkmgr_peri_clk_usbdev_aon_clk | Verify clkmgr's
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V2 | clkmgr_clk_io_div4_powerup | clkmgr_powerup_clk_clkmgr_clk clkmgr_powerup_clk_pinmux_clk clkmgr_powerup_clk_pwm_clk clkmgr_powerup_clk_pwrmgr_clk clkmgr_powerup_clk_rstmgr_clk clkmgr_powerup_clk_rstmgr_io4_clk | Verify clkmgr's
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V2 | clkmgr_clk_aon_powerup | clkmgr_powerup_clk_pinmux_aon_clk clkmgr_powerup_clk_pwm_core_clk clkmgr_powerup_clk_pwrmgr_slow_clk clkmgr_powerup_clk_rstmgr_aon_clk | Verify clkmgr's
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V2 | clkmgr_clk_main_powerup | clkmgr_powerup_clk_rstmgr_main_clk | Verify clkmgr's
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V2 | clkmgr_clk_io_powerup | clkmgr_powerup_clk_rstmgr_io_clk | Verify clkmgr's | |||||||||||||||||||||||||||||||||||||||||||||
V2 | clkmgr_clk_usb_powerup | clkmgr_powerup_clk_rstmgr_usb_clk | Verify clkmgr's | |||||||||||||||||||||||||||||||||||||||||||||
V2 | clkmgr_clk_io_div2_powerup | clkmgr_powerup_clk_rstmgr_io2_clk | Verify clkmgr's | |||||||||||||||||||||||||||||||||||||||||||||
V2 | clkmgr_clk_io_div4_secure | clkmgr_secure_clk_alert_handler_clk clkmgr_secure_clk_otp_ctrl_clk clkmgr_secure_clk_pwrmgr_clk clkmgr_secure_clk_rv_core_ibex_clk clkmgr_secure_clk_rv_core_ibex_otp_clk clkmgr_secure_clk_sensor_ctrl_clk clkmgr_secure_clk_ast_tlul_clk clkmgr_secure_clk_ast_alert_clk clkmgr_secure_clk_lc_ctrl_clk | Verify clkmgr's
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V2 | clkmgr_clk_main_secure | clkmgr_secure_clk_alert_handler_edn_clk clkmgr_secure_clk_ast_es_clk clkmgr_secure_clk_ast_rng_clk clkmgr_secure_clk_csrng_clk clkmgr_secure_clk_edn0_clk clkmgr_secure_clk_edn1_clk clkmgr_secure_clk_entropy_src_clk clkmgr_secure_clk_keymgr_clk clkmgr_secure_clk_keymgr_edn_clk clkmgr_secure_clk_lc_ctrl_kmac_clk clkmgr_secure_clk_otp_ctrl_edn_clk clkmgr_secure_clk_rv_plic_clk | Verify clkmgr's
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V2 | clkmgr_clk_aon_secure | clkmgr_secure_clk_ast_adc_clk clkmgr_secure_clk_sensor_ctrl_aon_clk | Verify clkmgr's
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V2 | clkmgr_clk_usb_secure | clkmgr_secure_clk_ast_usb_clk | Verify clkmgr's | |||||||||||||||||||||||||||||||||||||||||||||
V2 | clkmgr_clk_io_div4_timers | clkmgr_timers_clk_aon_timer_clk clkmgr_timers_clk_rv_timer_clk | Verify clkmgr's
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V2 | clkmgr_clk_aon_timers | clkmgr_timers_clk_aon_timer_aon_clk | Verify clkmgr's | |||||||||||||||||||||||||||||||||||||||||||||
V2 | flash_ast_obs_ctrl | flash_ast_obs_ctrl | Verify ast's | |||||||||||||||||||||||||||||||||||||||||||||
V2 | lc_escalate_en | lc_escalate_en_otp lc_escalate_en_aon_timer lc_escalate_en_sram_main lc_escalate_en_sram_ret lc_escalate_en_flash lc_escalate_en_aes lc_escalate_en_kmac lc_escalate_en_otbn | Verify lc_ctrl's
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V2 | pwrmgr_rst_lc_req | pwrmgr_rst_lc_req | Verify pwrmgr's | |||||||||||||||||||||||||||||||||||||||||||||
V2 | pwrmgr_rst_sys_req | pwrmgr_rst_sys_req | Verify pwrmgr's | |||||||||||||||||||||||||||||||||||||||||||||
V2 | rstmgr_rst_lc_src_n | rstmgr_rst_lc_src_n | Verify rstmgr's | |||||||||||||||||||||||||||||||||||||||||||||
V2 | rstmgr_rst_sys_src_n | rstmgr_rst_sys_src_n | Verify rstmgr's | |||||||||||||||||||||||||||||||||||||||||||||
V2S | tl_intg_err | chip_tl_intg_err chip_sec_cm | Verify that the data integrity check violation generates an alert.
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V3 | chip_sw_kmac_entropy | Verify the EDN interface to KMAC. Requires
TODO: This is pending security review discussion. It is unclear if this feature will be implemented. X-ref'ed with EDN test/env. |
Covergroups
Name | Description |
---|---|
regwen_val_when_new_value_written_cg | Cover each lockable reg field with these 2 cases:
This is only applicable if the block contains regwen and locakable CSRs. |
tl_errors_cg | Cover the following error cases on TL-UL bus:
|
tl_intg_err_cg | Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check. Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied. |
Testplan (Gate level simulations)
Note that the descriptions of the test below may be replicated from the table above.
Testpoints
Milestone | Name | Tests | Description |
---|---|---|---|
V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | Verify transmission of data over the TX and RX port. SW test sends a known payload over the TX port. The testbench, at the same time sends a known payload over RX. On reception, both payloads are checked for integrity. SW validates the reception of TX watermark, RX watermark, and the TX empty interrupts. Choosing the max supported baud rate for the UART is sufficient. Verify each UART instance at the chip level independently. Verify there is no aliasing on all UART ports across the instances. |
Covergroups
Name | Description |
---|---|
regwen_val_when_new_value_written_cg | Cover each lockable reg field with these 2 cases:
This is only applicable if the block contains regwen and locakable CSRs. |
tl_errors_cg | Cover the following error cases on TL-UL bus:
|
tl_intg_err_cg | Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check. Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied. |