TL-UL Checklist

This checklist is for Hardware Stage transitions for the TL-UL component. All checklist items refer to the content in the Checklist.

Design Checklist

D1

Type Item Resolution Note/Collaterals
Documentation SPEC_COMPLETE Done TL-UL Spec crossbar_tool
Documentation CSR_DEFINED N/A
RTL CLKRST_CONNECTED Done
RTL IP_TOP Done
RTL IP_INSTANTIABLE Done
RTL MEM_INSTANCED_80 N/A
RTL FUNC_IMPLEMENTED Done
RTL ASSERT_KNOWN_ADDED Done
Code Quality LINT_SETUP Done
Review Reviewer(s) Done @weicaiyang @aytong @martin-lueker
Review Signoff date Done 2019-11-04

D2

Type Item Resolution Note/Collaterals
Documentation NEW_FEATURES N/A
Documentation BLOCK_DIAGRAM Done
Documentation DOC_INTERFACE N/A
Documentation MISSING_FUNC N/A
Documentation FEATURE_FROZEN Done
RTL FEATURE_COMPLETE Done
RTL AREA_SANITY_CHECK Done
RTL PORT_FROZEN Done Targetting for current top_earlgrey( Port can be changed later based on top_earlgrey config)
RTL ARCHITECTURE_FROZEN Done
RTL REVIEW_TODO Done PR #837 is pending
RTL STYLE_X Done
Code Quality LINT_PASS Done
Code Quality CDC_SETUP N/A top_earlgrey uses single clock at this moment. (new PR by Tim is pending )
Code Quality FPGA_TIMING Done Pipeline inserted in front of Core IBEX. meet timing @ 50MHz on NexysVideo
Code Quality CDC_SYNCMACRO N/A
Review Reviewer(s) Done @sjgitty @weicaiyang
Review Signoff date Done 2019-11-04

D3

Type Item Resolution Note/Collaterals
Documentation NEW_FEATURES_D3 N/A
RTL TODO_COMPLETE Done Resolved: #837
Code Quality LINT_COMPLETE Done
Code Quality CDC_COMPLETE N/A
Review REVIEW_RTL Done 1st @tjaychen / 2nd @martin-lueker
Review REVIEW_DELETED_FF N/A
Review REVIEW_SW_CSR N/A
Review REVIEW_SW_FATAL_ERR Done
Review REVIEW_SW_CHANGE N/A
Review REVIEW_SW_ERRATA Done
Review Reviewer(s) Done @weicaiyang @tjaychen
Review Signoff date Done 2019-11-07

Verification Checklist

V1

Type Item Resolution Note/Collaterals
Documentation DV_PLAN_DRAFT_COMPLETED Done DV_PLAN
Documentation TESTPLAN_COMPLETED Done
Testbench TB_TOP_CREATED Done
Testbench PRELIMINARY_ASSERTION_CHECKS_ADDED Done
Testbench TB_ENV_CREATED Done
Testbench RAL_MODEL_GEN_AUTOMATED N/A
Testbench TB_GEN_AUTOMATED Waived Manually generated. Planned to automate later
Tests SANITY_TEST_PASSING Done
Tests CSR_MEM_TEST_SUITE_PASSING N/A
Tool Setup ALT_TOOL_SETUP Done
Regression SANITY_REGRESSION_SETUP Done Exception (Runs at local)
Regression NIGHTLY_REGRESSION_SETUP Done Exception (Runs at local)
Coverage COVERAGE_MODEL_ADDED Done
Integration PRE_VERIFIED_SUB_MODULES_V1 Waived prim_arbiter to be verified later
Review DESIGN_SPEC_REVIEWED Done
Review DV_PLAN_TESTPLAN_REVIEWED Done
Review STD_TEST_CATEGORIES_PLANNED Done Exception (Security, Power, Debug, Performance)
Review V2_CHECKLIST_SCOPED Done
Review Reviewer(s) Done @eunchan @sjgitty @sriyerg
Review Signoff date Done 2019-11-04

V2

Type Item Resolution Note/Collaterals
Documentation DESIGN_DELTAS_CAPTURED_V2 N/A
Documentation DV_PLAN_COMPLETED Done
Testbench ALL_INTERFACES_EXERCISED Done
Testbench ALL_ASSERTION_CHECKS_ADDED Done
Testbench TB_ENV_COMPLETED Done
Tests ALL_TESTS_PASSING Done
Tests FW_SIMULATED N/A
Regression NIGHTLY_REGRESSION_V2 Done
Coverage CODE_COVERAGE_V2 Done
Coverage FUNCTIONAL_COVERAGE_V2 Done
Issues NO_HIGH_PRIORITY_ISSUES_PENDING Done
Issues ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED Done
Integration PRE_VERIFIED_SUB_MODULES_V2 Waived prim_arbiter to be verified later
Review V3_CHECKLIST_SCOPED Done
Review Reviewer(s) Done @eunchan @sjgitty @sriyerg
Review Signoff date Done 2019-11-04

V3

Type Item Resolution Note/Collaterals
Documentation DESIGN_DELTAS_CAPTURED_V3 N/A
Testbench ALL_TODOS_RESOLVED Done
Tests X_PROP_ANALYSIS_COMPLETED Waived tool setup in progress
Regression NIGHTLY_REGRESSION_AT_100 Done
Coverage CODE_COVERAGE_AT_100 Done xbar_cov_excl.el
Coverage FUNCTIONAL_COVERAGE_AT_100 Done
Issues NO_ISSUES_PENDING Done
Code Quality NO_TOOL_WARNINGS_THROWN Done Waived warning due to using ‘force’ to connect the signal
Integration PRE_VERIFIED_SUB_MODULES_V3 Waived prim_arbiter to be verified later
Review Reviewer(s) Done @eunchan @sriyerg
Review Signoff date Done 2019-11-07