Hardware Dashboard

This page serves as the landing spot for all hardware development within the OpenTitan project.

We start off by providing links to the results of various tool-flows run on all of our Comportable IPs. This includes DV simulations, FPV and lint, all of which are run with the dvsim tool which serves as the common frontend.

The Comportable IPs following it provides links to their design specifications and DV documents, and tracks their current stage of development. See the Hardware Development Stages for description of the hardware stages and how they are determined.

Next, we focus on all available processor cores and provide links to their design specifications, DV documents and the DV simulation results.

Finally, we provide the same set of information for all available top level designs, including an additional dashboard with preliminary synthesis results for some of these designs.

Results of tool-flows

Comportable IPs

Design Spec DV Document Spec Version Development Stage Notes
adc_ctrl DV 1.0 L1 D2S V2S S0

 
aes DV 1.0 L1 D2S V2 S2
aon_timer DV 1.0 L1 D2S V2 S2

 
clkmgr DV 1.0 L1 D2S V2 S2

 
csrng DV 1.0 L1 D2S V1 S2

 
edn DV 1.0 L1 D2S V1 S0

 
entropy_src DV 1.0 L1 D2S V1 S0

 
flash_ctrl DV 0.1 L1 D1 V1 -

 
1.0 L1 D2S V1 S0

 
gpio DV 1.0 L2 D3 V3 -

 
1.1 L1 D2S V2 S2

 
hmac DV 0.5 L2 D3 V3 -

 
1.0 L1 D2S V2 S1

Rolled back to D2 in order to add the first alert
i2c DV 1.0 L1 D2S V1 S0

 
keymgr DV 1.0 L1 D2S V2 S0

 
kmac DV 1.0 L1 D2S V2 S2

 
lc_ctrl DV 1.0 L1 D3 V2S S0
otbn DV 0.1 L1 D1 V1 S1

 
1.0 L1 D2 V2 S2

 
otp_ctrl DV 0.1 L1 D2 V2 S1

 
1.0 L1 D2S V2S S2

Will fully support test_access tl_if once reggen tool is optimized.
pattgen DV 1.0 L1 D2S V2S S0

 
pinmux DV 1.0 L1 D2S V2 S0

Use FPV to perform block level verification.
pwm DV 1.0 L1 D2S V1 S0

 
pwrmgr DV 0.1 L1 D1 V0 S0

 
1.0 L1 D2S V2 S2

 
rom_ctrl DV 1.0 L1 D2S V2S S0

 
rstmgr DV 1.0 L1 D2S V2 S2

 
rv_core_ibex DV 1.0 L1 D2S V1 S2

 
rv_dm DV 1.0 L1 D2S V1 -

 
rv_timer DV 0.5 L2 D3 V3 -

 
1.0 L1 D2S V2 S2

 
spi_device DV 0.5 L1 D1 V1 S0

 
1.0 L1 D2S V1 S0

 
spi_host DV 1.0 L1 D2S V1 S2

 
sram_ctrl DV 1.0 L1 D2S V2S S2
sysrst_ctrl DV 1.0 L1 D2S V2S S0

 
tlul DV 0.5 L2 D3 V3 -

The target for this entry is the autogenerated xbar_main within top_earlgrey.
1.0 L1 D2 V2 -

Only the XBAR instances (xbar_main and xbar_peri) and TLUL components that go into them are certified to V2. For exceptions see DV_DOC
uart DV 1.0 L2 D3 V3 -

 
1.1 L1 D2S V2 S2

 
usbdev DV 1.0 L1 D2S V0 S1

 

Processor cores

Earl Grey toplevel design

Earl Grey-specific comportable IPs

Design Spec DV Document Spec Version Development Stage Notes
alert_handler DV 1.0 L1 D2S V2 S2

Use both FPV and DV to perform block level verification.
rv_plic DV 1.0 L1 D2S V2 S2

Use FPV to perform block level verification.
sensor_ctrl DV 1.0 L1 D2 N/A -

Verified at the top-level.

Hardware documentation overview