Hardware Dashboard

This page serves as the landing spot for all hardware development within the OpenTitan project.

We start off by providing links to the results of various tool-flows run on all of our Comportable IPs. This includes DV simulations, FPV and lint, all of which are run with the dvsim tool which serves as the common frontend.

The Comportable IPs following it provides links to their design specifications and DV documents, and tracks their current stage of development. See the Hardware Development Stages for description of the hardware stages and how they are determined.

Next, we focus on all available processor cores and provide links to their design specifications, DV documents and the DV simulation results.

Finally, we provide the same set of information for all available top level designs, including an additional dashboard with preliminary synthesis results for some of these designs.

Results of tool-flows

Comportable IPs

Design Spec DV Plan Version Development Stage Notes
adc_ctrl DV 1.0 L1 D0 V0 -

DV resource allocation pending.
aes DV 1.0 L1 D1 V1 S0

D2 except for SEC_CM_IMPLEMENTED; SCA/FI hardening in progress
alert_handler DV 0.5 L1 D1 V1 S0

will be verified at top level; formal and DV at block level
aon_timer DV 1.0 L1 D1 V0 S1

 
clkmgr DV 0.1 L1 D2 V1 S1

 
csrng DV 0.5 L1 D2 V1 -

 
edn DV 0.5 L1 D2 V1 -

 
entropy_src DV 0.5 L1 D1 V1 -

 
flash_ctrl DV 0.1 L1 D1 V1 -

 
0.5 L1 D2 V1 -

DV resource allocation pending.
gpio DV 1.0 L2 D3 V3 -

 
1.1 L1 D2 V2 S1

Rolled back to D2 as the register module is updated
hmac DV 0.5 L2 D3 V3 -

 
0.6 L1 D2 V1 S0

Rolled back to D2 in order to add the first alert
i2c DV 0.5 L1 D1 V1 S0

 
keymgr DV 0.1 L1 D1 V1 -

 
kmac DV 1.0 L1 D1 V1 -

Reaching V1
lc_ctrl DV 0.1 L1 D1 V1 -
nmi_gen 0.5 L1 D0 V0 -

will be verified at top level; formal at block level
otbn DV 0.1 L1 D1 V1 S1

 
0.2 L1 D1 V1 S1

 
otp_ctrl DV 0.1 L1 D2 V2 S1
pattgen DV 1.0 L1 D1 V1 S0

 
pinmux DV 0.5 L1 D1 V0 -

will be verified at top level; formal at block level
pwm DV 1.0 L1 D1 V0 S0

 
pwrmgr DV 0.1 L1 D1 V0 S0

 
0.5 L1 D2 V0 S0

 
rom_ctrl DV 0.1 L1 D0 V0 -

 
rstmgr DV 0.1 L1 D2 V0 S1

 
rv_core_ibex 0.5 L1 D2 V1 -

 
rv_dm 0.5 L1 D1 V0 -

 
rv_plic DV 0.5 L1 D2 V2 S1

based on FPV at block level
rv_timer DV 0.5 L2 D3 V3 -

 
0.6 L1 D2 V2 S0

Rolled back to D2 as the register module is updated
spi_device DV 0.5 L1 D1 V1 S0

 
spi_host 0.5 L0 - - -

 
sram_ctrl DV 0.1 L1 D2 V1 -
sysrst_ctrl DV 1.0 L1 D0 V0 -

DV resource allocation pending.
tlul DV 0.5 L2 D3 V3 -

the target for this entry is the autogenerated xbar_main within top_earlgrey.
1.0 L1 D1 V1 -

 
uart DV 1.0 L2 D3 V3 -

 
1.1 L1 D2 V2 S1

Rolled back to D2 as the register module is updated
usbdev DV 0.5 L1 D1 V0 S0

DV resource allocation pending.

Processor cores

Top level designs

Hardware documentation overview